1. Field of the Invention
The invention relates to a method for operation of a flash memory, and more particularly, to a method to improve accuracy of a low voltage state in flash memory cells.
2. Description of Related Art
A non-volatile memory, such as a flash memory, generally includes a stacked gate constituted by a floating gate and a control gate. A dielectric layer is placed between the floating gate and the control gate, and a tunnel oxide layer is located between the floating gate and a substrate. The floating gate is located between the substrate and the control gate, and is in a “floating” state (i.e., not electrically connecting to any circuits). The control gate is electrically connected to a word line. The floating gate is configured to store electrical charges, and the control gate is configured to control a data write/read operation. A memory cell with structure of the floating gate may be used as a single-bit or a multi-bit memory cell and so on.
It is required to add or remove the electrical charges limited in the floating gate during a program and erase operation to the memory cell of the flash memory, and characteristics of the memory cell in terms of reading, programming and erasing may be changed by such accumulation and removal of the electrical charges over time in said regions. Eventually, the accumulation of the electrical charges changes a threshold voltage for determining a state of the memory cell. Said problem is caused by a threshold voltage shift in the memory cell generally known as a disturbance phenomenon. Further, a charge loss of the memory cell after repeatedly cycling also leads to the threshold voltage shift (especially to a programming threshold voltage) and a performance degradation. Changes in the threshold voltage due the disturbance and/or the charge loss may affect a memory device in correctly sensing a bit state. Afore-said problem becomes even more notable when the memory cells are constantly scaled down and a distance between each two of the word lines gets too close.
In the program and erase operation of the flash memory, it is required to compare a value (e.g., a voltage level of a data bit) from a memory unit with a reference value, so as to determine each bit state (including a program state or an erase status) as stored in the single-bit or the multi-bit memory cell. Generally, during initial manufacturing period, a reference unit is pre-programmed and set to the erasing state for providing the reference value stably. When the value from the memory unit is greater than the reference value, it is determined that the memory unit is in the program state. On the other hand, when the value from the memory unit is less than the reference value, it is then determined that the memory unit is in the erase state.
FIG. 1 is a diagram illustrating a sensing window of a memory unit. A line 102 represents an ideal programming threshold voltage of the memory unit over time. A line 104 represents an example of the programming threshold voltage of the memory unit being changed over time and taken in consideration of the bit disturbance and the charge loss. A line 106 represents an ideal erasing threshold voltage of the memory unit over time. A line 108 represents an example of the erasing threshold voltage of the memory unit changed over time and taken in consideration of the bit disturbance and the charge loss. A line 110 represents a reference value provided by the reference unit of the memory device in conventional art, which is maintained at a constant value over time as shown in FIG. 1. Referring to FIG. 1, due to effects such as the bit disturbance and/or charge loss, a sensing window 112 between the reference value 110 and the programming threshold voltage 104 is reduced over time, and this may increase a possibility of sensing errors while lowering a reliability of the memory device.
In some applications, the erase operation must first be performed to the flash memory during the program operation. Such erase operation is mainly performed a cell array of the entire flash memory, individual blocks or a group of the memory cells. During the erase operation, an erase pulse is usually adopted to shift the threshold voltage of the memory cell to an erase target level. In some applications, after the erase pulse is applied, an erase verify operation is performed to verify whether the entire array, blocks, or the entire group of the memory cells are completely erased. The procedure of applying the erase pulse and performing the erase verify operation is constantly performed until the entire erase procedure is completed. However, during the erase operation, a specific proportion of tail bits or stubborn bits are existed in the entire array, blocks or the entire group of memory cell, which cannot pass the erase verify operation after the erase pulse is applied. This situation will cause the time delayed to complete the erase operation.
With effects of the disturbance and the electrical charges accumulation, or other influences, the erasing threshold voltage of the memory cell may be changed over time. Changes of the threshold voltage over time may lead to a condition in which storage state of the memory cell cannot be determined in a read verify operation. In other case that more and more tail bits or the stubborn bits located in a high boundary of the low voltage threshold (LVT) state memory cells, it will cause the time be delayed to complete the erase operation. Such condition may be solved by increasing the operation window (including operation windows for the program and erase operation). Nevertheless, as the memory cell of the flash memory being constantly scaled down, or under multi-bit operations, said solution can no longer satisfies current demands.